\doxysection{SWPMI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_s_w_p_m_i___type_def}{}\label{struct_s_w_p_m_i___type_def}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}}


Single Wire Protocol Master Interface SPWMI.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_aecc2dc56573d57f5f476c380892ea2e2}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a24dca3d3fef0dbae21b72d6c9f98ac82}{BRR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a96cbc61176016e59e5f221a6f5883420}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a74f559fbb6982164f17b971ddfff705c}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_af29489661b1cc547d5a61c7798a89f69}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_acf541fac1b5a52320d3d4306f5e81dd8}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a16d5b62f16b36dda2c3c37cdb34dc335}{RFL}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a717971a9ac0ea8710ad884efd6eb8b0b}{TDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_a3084e031419c7432cb0b79ac256bc308}{RDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_w_p_m_i___type_def_aa70799e3ee75fd0a748b46139ee69d4f}{OR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Single Wire Protocol Master Interface SPWMI. 

\label{doc-variable-members}
\Hypertarget{struct_s_w_p_m_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_w_p_m_i___type_def_a24dca3d3fef0dbae21b72d6c9f98ac82}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!BRR@{BRR}}
\index{BRR@{BRR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BRR}{BRR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a24dca3d3fef0dbae21b72d6c9f98ac82} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+BRR}

SWPMI bitrate register, Address offset\+: 0x04 \Hypertarget{struct_s_w_p_m_i___type_def_aecc2dc56573d57f5f476c380892ea2e2}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!CR@{CR}}
\index{CR@{CR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_aecc2dc56573d57f5f476c380892ea2e2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+CR}

SWPMI Configuration/\+Control register, Address offset\+: 0x00 \Hypertarget{struct_s_w_p_m_i___type_def_af29489661b1cc547d5a61c7798a89f69}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_af29489661b1cc547d5a61c7798a89f69} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+ICR}

SWPMI Interrupt Flag Clear register, Address offset\+: 0x10 \Hypertarget{struct_s_w_p_m_i___type_def_acf541fac1b5a52320d3d4306f5e81dd8}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!IER@{IER}}
\index{IER@{IER}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_acf541fac1b5a52320d3d4306f5e81dd8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+IER}

SWPMI Interrupt Enable register, Address offset\+: 0x14 \Hypertarget{struct_s_w_p_m_i___type_def_a74f559fbb6982164f17b971ddfff705c}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a74f559fbb6982164f17b971ddfff705c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+ISR}

SWPMI Interrupt and Status register, Address offset\+: 0x0C \Hypertarget{struct_s_w_p_m_i___type_def_aa70799e3ee75fd0a748b46139ee69d4f}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!OR@{OR}}
\index{OR@{OR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OR}{OR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_aa70799e3ee75fd0a748b46139ee69d4f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+OR}

SWPMI Option register, Address offset\+: 0x24 \Hypertarget{struct_s_w_p_m_i___type_def_a3084e031419c7432cb0b79ac256bc308}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!RDR@{RDR}}
\index{RDR@{RDR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RDR}{RDR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a3084e031419c7432cb0b79ac256bc308} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+RDR}

SWPMI Receive data register, Address offset\+: 0x20 \Hypertarget{struct_s_w_p_m_i___type_def_a96cbc61176016e59e5f221a6f5883420}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a96cbc61176016e59e5f221a6f5883420} 
uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, 0x08 \Hypertarget{struct_s_w_p_m_i___type_def_a16d5b62f16b36dda2c3c37cdb34dc335}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!RFL@{RFL}}
\index{RFL@{RFL}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RFL}{RFL}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a16d5b62f16b36dda2c3c37cdb34dc335} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+RFL}

SWPMI Receive Frame Length register, Address offset\+: 0x18 \Hypertarget{struct_s_w_p_m_i___type_def_a717971a9ac0ea8710ad884efd6eb8b0b}\index{SWPMI\_TypeDef@{SWPMI\_TypeDef}!TDR@{TDR}}
\index{TDR@{TDR}!SWPMI\_TypeDef@{SWPMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TDR}{TDR}}
{\footnotesize\ttfamily \label{struct_s_w_p_m_i___type_def_a717971a9ac0ea8710ad884efd6eb8b0b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SWPMI\+\_\+\+Type\+Def\+::\+TDR}

SWPMI Transmit data register, Address offset\+: 0x1C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
